发明名称 INTERNAL MEMORY CONTROL SYSTEM ON ARRAY PROCESSOR
摘要 PURPOSE:To make it possible to process vector data composed of a number of elements in a high speed by dividing an internal memory into a number of memory banks which can be acessed independently. CONSTITUTION:One internal memory is constituted by addressing four memory banks 11-0 to 11-3 as shown in the figure. Here, 12, 13, 14 and 15 indicate B operand bus, C operand bus, instruction bus and A operand bus respectively. When vector operation ''A B X C'' is performed, read of B operand and C operand, write of A operand, and read of instruction can be executed simultaneously.
申请公布号 JPS5491151(A) 申请公布日期 1979.07.19
申请号 JP19770159063 申请日期 1977.12.28
申请人 FUJITSU LTD 发明人 MATSUMOTO YASUO;UCHIDA KEIICHIROU;ETSUNO MINORU;TANAKA TSUTOMU
分类号 G06F17/16;G11C7/00;(IPC1-7):11C7/00 主分类号 G06F17/16
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