发明名称 DIGITAL INFORMATION PROCESSOR
摘要 A circuit is disclosed for serially formatting digital information such as may be provided in a digital audio magnetic tape recorder in a succession of data blocks or frames, each containing the same number of digital bits and in which each frame is delineated by a uniquely occurring digital frame synchronizing signal. The digital information is formatted in a Miller or 3F code in which allowable transitions between successive "1"s and "0"s result in pulses which are 1, 1-1/2 or 2 times the duration of a bit cell, hence giving rise to three characteristic frequencies and the term 3F code. The frame synchronizing signal is generated by providing a signal comprising digital bits 1-0-0-1, which signal in a 3F code is characterized by a transition between the adjacent "0"s, and by appropriately inhibiting that transition, thus creating a pulse which is three times the duration of a unit cell, hence giving rise to a new fourth frequency which cannot be normally created by any succession of "1"s or "0"s.
申请公布号 JPS5474717(A) 申请公布日期 1979.06.15
申请号 JP19780135137 申请日期 1978.11.01
申请人 MINNESOTA MINING & MFG 发明人 PIITAA AMASU
分类号 H03M5/12;G11B20/12;G11B20/14;H03M7/00;H04J3/06;H04L7/00;H04L7/06;H04L7/08;H04L25/40;H04L25/49 主分类号 H03M5/12
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