| 摘要 |
The method and circuitry for detecting two different binary numbers or digital words in a register or counter using logic gates wherein bits are detected using n-1 logic gates when all the digits of each of words or numbers are at the same one of a plurality of possible logic levels. In other words, two numbers such as all logic ones as the first number and all logic zeros as the second number. Specifically, this concept is applied to checking an up-down counter output so that it is prevented from overflowing or underflowing by stopping it at either a count of all logic zeros or all logic ones.
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