| 摘要 |
PURPOSE:To make it possible to attain access to memory array body at a high speed, by using semiconductor memory elements whose impedance at the output terminal varies at the time of reading data and by shortening the time difference between the memory output generation and strobe signal generation. CONSTITUTION:Several semiconductor memory elements 2 are provided whose output terminals become low in impedance at the time of reading and high at the time of non-reading, and impedance detection circuits 5-1, 5-2...5-n are also provided which discriminate the variation in impedance amon several bit lines 3-1, 3-2...3-n connected to output terminals of elements 2 and bit lines 3-1, 3-2...3-n provided to respective bit lines 3-1, 3-2...3-n. Further, AND circuit 6 is provided which discriminates that bit lines 3-1, 3-2...3-n are all low in impedance by being supplied with output signals from detection circuits 5-1, 5-2...5-n. |
