发明名称 Method for forming contact vias in integrated circuits.
摘要 <p>A structure and method for forming contact vias in integrated circuits. An interconnect layer is formed on an underlying layer in an integrated circuit. A buffer region is then formed adjacent to the interconnect layer, followed by forming an insulating layer over the integrated circuit. Preferably, the insulating layer is made of a material which is selectively etchable over the material in the buffer region. A contact via is then formed through the insulating layer to expose a portion of the interconnect layer. During formation of the contact via, the buffer region acts as an etch stop and protects the underlying layer. The buffer region also ensures a reliable contact will be made in the event of an error in contact via placement. &lt;IMAGE&gt;</p>
申请公布号 EP0568385(A2) 申请公布日期 1993.11.03
申请号 EP19930303406 申请日期 1993.04.30
申请人 SGS-THOMSON MICROELECTRONICS, INC. 发明人 HASLAM, MICHAEL EDWARD;SPINNER III, CHARLES RALPH
分类号 H01L21/30;H01L21/027;H01L21/3205;H01L21/768;H01L23/52;(IPC1-7):H01L21/90 主分类号 H01L21/30
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