发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
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申请公布号 |
US2008072095(A1) |
申请公布日期 |
2008.03.20 |
申请号 |
US20070936543 |
申请日期 |
2007.11.07 |
申请人 |
NAMBU HIROAKI;SHINOZAKI MASAO;KANETANI KAZUO;KAZAMA HIDETO |
发明人 |
NAMBU HIROAKI;SHINOZAKI MASAO;KANETANI KAZUO;KAZAMA HIDETO |
分类号 |
G06F1/06;G06F1/12;G06F1/04;G06F13/42;G11C11/40;G11C11/407;H03K5/13;H04L5/00;H04L7/00;H04L7/04 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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