发明名称 Logic circuit using CMOS transistors
摘要 A logic circuit using CMOS transistors, in which electrical power is supplied to a CMOS logic circuit that is formed of P-channel type and N-channel type MOS transistors by way of a depletion type MOS transistor. The output level with respect to the voltage of the power source that is used is set at some point by the design of the depletion-type MOS transistor.
申请公布号 US4122360(A) 申请公布日期 1978.10.24
申请号 US19770820118 申请日期 1977.07.29
申请人 TOKYO SHIBAURA ELECTRIC COMPANY, LIMITED 发明人 KAWAGAI, KENJI;YOSHIDA, SHIGEKI
分类号 H03K17/04;H03K19/0948;H03K19/096;(IPC1-7):H03K19/08;H03K19/40;H03K19/20 主分类号 H03K17/04
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