| 摘要 |
A memory access control system is provided between one or more accessing devices and a main memory composed of a plurality of independently accessible logical storages, and receives a request from the accessing device and, based on the status of the main memory, permits access to one of the logical storages. The memory access control system comprises a shift register, composed of stages corresponding to the cycle time of the main memory, for storing address information sufficient for identifying a busy one of the logical storages and for sequentially shifting the stored content in synchronism with a clock signal, and a comparator circuit for comparing the content of each stage of the shift register with address information of the logical storage designated based on the request from the accessing device, receiving the request based on the result of the comparison, and generating a control signal for accessing the designated logical storage. Using the shift register, one of the logical storages to be accessed can be checked whether it is busy or not, so that even if the number of logical storages is increased with an increase of the capacity of the main memory, the scale of the memory access control system is not enlarged. The shift register also has stored therein the codes of operations, the codes of the accessing devices, etc., and is capable of identifying the accessing device to which data read out from the main memory is to be sent back, and of achieving a partial write control.
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