Central processor interface to sub-units - acts via universal interfaces requiring no circuitry change for different units

摘要

A device with a central data processor (1) and connected sub-units (6) is developed to enable connection of an optional selection from a universal cross-section of sub-units to the processor without variation in the interface circuits. The sub-units each have inputs and/or outputs for direct bit-serial data transfer to and/or from another unit at fixed data rate. These inputs and/or outputs are each connected to central processor inputs and/or outputs in parallel. They may be switched to a high impedance condition under control of a signal on a special address channel from the processor.