| 摘要 |
PURPOSE:To prevent vanish of timing information for clock reproduction, by causing level inversion once in every 3-bit when a DMI code is converted into tri-state AMI code at reception side, even if consecutive ''0''s are caused in the NRZ code at transmission side. CONSTITUTION:When ''0''s are consecutive by 3-bit in the NRZ code inputted at a ''0'' consecution detecting circuit 6, if the number of data ''1''s of NRZ code inputted through the count of consecutive ''0''s detected previously at a pattern insertion circuit 7 is an even number, ''000'' is converted into ''011'' and in case of an odd number, ''000'' is converted into ''111'' and the result is inputted to a DMI coding circuit 8. The circuit 8 makes coding it according to the code rule, and makes the polarity of the ''1'' at the 3rd bit to the polarity of just before the DMI code according to a violation signal V outputted from a pattern insertion circuit 7 to inform that the code rule of the DMI code is violated and the said conversion is made to the reception side. |
