Fault detection in counter circuits - using three bistable stages which maintain steady output if fault arises in counter stages

摘要

A fault detection circuit based upon bistable devices is used to indicate malfunctions in counter circuits. Two counter stages are tested by being driven by clock pulses displaced such that output signals are overlapped. The outputs of one stage is used to enable the first bistable within the fault detection stage. The output from the last stage is coupled with the output from the second counter stage and is used to control the bistable. Two other bistables are also subsequently set. Once the bistables have been cycled a steady 'O' output from the detection stage results if there is a fault in the operation of the counter stages.