| 摘要 |
PURPOSE:To protect a write unable memory area by inhibiting the memory writing operation when a control signal generating circuit produces its output and at the same time fetching the memory access address to an address latch. CONSTITUTION:An upper limit address comparator 16 produces its output when the address set on an address bus AB is less than the upper limit address set at an upper limit address latch 12. A lower limit address comparator 18 produces its output when the address set on the bus AB is higher than the lower limit address set at a lower limit address latch 14. Therefore an AND gate G1 produces its output as long as the addresses set on the bus AB are kept within the ranges of the upper and lower addresses respectively. Then an AND gate G2 produces its output in its memory writing state. A control signal generating circuit 22 receives the output of the gate G2 to output a signal and inhibits the transmission of a memory write signal WS via an output control circuit 20. Thus the writing operations are inhibited to a write unable memory area and the destruction of the storage information is prevented in this memory area. |
