发明名称 00 CUT ADDER WITH PREVENTION SIGNAL
摘要 PROBLEM TO BE SOLVED: To manufacture a 00 cut adder with a prevention signal which prevents an error signal. SOLUTION: An AND1H carrier signal of one digit is inputted to a C41 line→a diode di3→an intersection p4→4 digit AND, E1 (5) and an AND, E0 (6) and a NOR, and N7, and E1, E0 and N output are inputted to an OR and R8. 00 and an L signal prepared by an OR 9 of intermediate 2 and 3 digits are inputted to C41 (2) through di10, an output of an AND 11 is inputted to E1 and N, and an output of a NOR 13 is inputted to E0 (6) and N. The collector of a transistor TR15 is connected to ground, C41 (2) is connected to a base b6 through di18, and (b) is connected to ground through resistance r17. An emitter line n20 is inputted to N7, a NOR 19 output is inputted to b23 through di20, (b) is connected to 5 volt though resistance 22, and (n) input 26 is made H until (p) comes to H.
申请公布号 JP2000181684(A) 申请公布日期 2000.06.30
申请号 JP19980366025 申请日期 1998.11.16
申请人 SUGIMURA YUKICHI 发明人 SUGIMURA YUKICHI
分类号 G06F7/50;G06F7/499;G06F7/508;(IPC1-7):G06F7/50 主分类号 G06F7/50
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