| 摘要 |
<p>The frequency-analog desired and actual-value signals are applied to a subtractor stage, which forms the difference between the frequencies of the two signals, and this difference is superimposed on a carrier frequency. The output frequency is compared with the carrier frequency in a two-bit reversible counter, whose output is a pulse-width modulated output pulse train which forms the correction signal. A proportional component can be introduced in that the difference frequency modulates the phase of the carrier pulse train before the comparison. A subordinate control loop can be formed in that the output signal of the comparison-counter applies a reference frequency to a further reversible counter, which at the input for the other direction continuously receives the frequency-analog further actual-value signal. The output signal of the further counter may then be further processed in digital or analog form. The further actual-value signal can also be converted into a pulse-width modulated signal, which can directly be compared with the other signal.</p> |
