发明名称 Instruction based interrupt masking for managing interrupts in a computer environment
摘要 Managing interrupts in a computing environment includes executing an instruction, deriving an interrupt mask value based at least in part on the instruction being executed, performing a masking operation involving the interrupt mask value and at least one pending interrupt to determine whether a pending interrupt is allowable, and in the event that the pending interrupt is allowable, performing the interrupt.
申请公布号 US9361114(B1) 申请公布日期 2016.06.07
申请号 US200511296651 申请日期 2005.12.06
申请人 Azul Systems, Inc. 发明人 Tene Gil;Sellers Scott;Choquette Jack;Wolf Michael A.
分类号 G06F7/38;G06F9/00;G06F9/44;G06F15/00;G06F9/38;G06F9/48 主分类号 G06F7/38
代理机构 Van Pelt, Yi & James LLP 代理人 Van Pelt, Yi & James LLP
主权项 1. A method of managing interrupts in a computing environment, comprising: executing an instruction, wherein the instruction comprises a native instruction included in a set of native instructions used to emulate a virtual instruction; selecting, from a plurality of interrupt masks, an appropriate, corresponding interrupt mask for the native instruction being executed, wherein: representations of at least a portion of the plurality of interrupt masks were previously stored in a table, and wherein the table specifies a mapping of each type of native instruction in the set of native instructions to a particular interrupt mask included in the plurality of interrupt masks;a given interrupt mask in the plurality of interrupt masks is associated with a corresponding bit pattern representing a corresponding set of allowable and disallowable types of interrupts, wherein each bit in the bit pattern indicates whether a corresponding type of interrupt is allowable; andselecting the appropriate, corresponding interrupt mask for the native instruction being executed includes performing a lookup of the table based at least in part on the type of the native instruction being executed; subsequent to selecting the appropriate, corresponding interrupt mask, determining, based at least in part on a masking operation involving the selected interrupt mask, whether each pending type of interrupt in a set of one or more pending types of interrupts is allowable at least in part by checking a corresponding bit in the bit pattern associated with the selected interrupt mask; and in the event that a pending type of interrupt is determined to be allowable, performing the pending type of interrupt.
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