Access enablement security circuit

摘要

A system-on-chip (SoC) is provided that includes a centralized access enablement circuit for controlling access to a plurality of security features for multiple hardware modules of the system. Progressive security states corresponding to different stages in a chip's design, manufacture and delivery are utilized to enable different access control settings for security features as a part moves from design to end-use. The access enablement circuit for a SoC implementing different security states provides individual access control settings for security features in the different security states. One-time programmable memory and register controls are provided in one embodiment that allow different access control settings for an individual security feature in the same or different security states of the system.

主权项

1. A system-on-chip, comprising:
a plurality of hardware modules implemented on a silicon substrate, the plurality of hardware modules configured for communication over one or more buses; a plurality of security features provided by the plurality of hardware modules; a one-time programmable memory storing information to indicate a progression of a plurality of security states for the system-on-chip; a first memory including a default access control setting for each security feature in each security state; a set of registers configured to store register data corresponding to the plurality of security features; a second memory configured to provide an override signal indicating whether the register data is to override the default access control setting for each security feature; and a centralized access enablement (AEB) circuit configured to control access to the plurality of security features, the centralized AEB circuit including a plurality of outputs, each output corresponding to a security feature of the hardware modules and configured to control access to the security feature, the centralized AEB circuit is configured to provide the output corresponding to a security feature based on an output of the set of registers for an active security state in response to the override signal being asserted.