| 摘要 |
A rate one-half random error convolutional coding system corrects the theoretical limit of one error out of four successive bits. An information bit stream is processed through the system encoder which is comprised of a two-bit shift register and a modulo-2 adder. The encoder generates a parity bit formed by the modulo-2 summing of successive pairs of information bits, and produces a convolved transmission bit stream. The system decoder is the replica of the encoder in combination with a two-bit syndrome register, an AND gate, complementary feedback circuitry, and an output modulo-2 adder.
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