| 摘要 |
In a pipelined data processor, each processing stage is provided with its own copies of relevant machine registers. Whenever a processing stage updates a register, it sets a flag. The flags and register copies are shifted along in step with the flow instructions down the pipeline. These flags are used to control multiplexers which ensure that each stage is provided with the most up-do-date copy of each register, taking into account any updates by succeeding stages. |
