| 摘要 |
1481049 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 15 Oct 1974 [1 Nov 1973] 44716/74 Heading H1K IGFETs having respectively fixed and variable thresholds are formed in a same semiconductor body by a process involving the application to the body of a series of insulating layers adjacent ones of which have different etch characteristics, selectively etching the layers through a sequence of masks to determine the transistor locations, diffusing source and drain regions into the previously defined locations of the body, selectively removing the insulating layers from the gate region of the fixed threshold transistor and growing a gate oxide thereon while retaining the lower two of the insulating layers in the gate region of the variable threshold transistor, and applying source, drain and gate electrodes to the two devices. In the illustrated process a P type Si epitaxial layer 12 on an N type substrate 11 is oxidized to provide a first 40-70 Š thick SiO 2 layer 13 and is then coated with alternate layers 14, 16 of CVD Al 2 O 3 600 Š thick and 15, 17 of pyrolytic SiO 2 700 Š thick. Openings 21, 22, 31, 32, to define source and drain areas of the two IGFETs, and 40, to define an isolating region therebetween, are etched through the upper two layers 17, 16 and a non-critically aligned mask is then used to cover the openings 21, 22, 31, 32 while the opening 40 is extended through the layers 15, 14 to the layer 13. At this point P or As is diffused to form the isolation region 44, the SiO 2 layer 13 being too thin to impede diffusion. The structure is then as shown in Fig. 1D. All the exposed SiO and the consequently exposed Al 2 O 3 is next removed, and source and drain regions 23, 24, 33, 34 are diffused through the windows thus opened down to the thin, non-masking layer 13. During this diffusion the isolation region 44 extends downwards to meet the substrate 11. A non-critically aligned mask is used to protect all of the remaining layers 14, 15 except over the gate area of the fixed threshold device and after the latter portions have been removed a thick SiO 2 layer is deposited over the entire structure. This merges with the remaining portions of layers 13 and 15 to form a SiO 2 layer 48 (Fig. II). A further non-critically masked etching step removes the layer 48 from the source, drain and gate areas of the fixed threshold IGFET and a fresh gate oxide layer 49 is grown there. Finally source and drain contact windows are opened and Al electrodes 55-60 (Fig. 1K) are applied. The left-hand IGFET of Fig. 1K is thus a conventional SiO 2 -gate fixed threshold device while the right-hand IGFET is an Al 2 O 3 -on-SiO 2 -gate variable threshold device.
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