| 摘要 |
Apparatus for timing the occurrence of a variety of control signals by using a storage device forming a pair of registers at each of a plurality of addressable locations and storing in one register a constant value while its corresponding register serves as an accumulator. A repetitive sequence of clock signals is continuously generated and each signal in a sequence is peculiar to a set of one or more addresses and, with other preconditions is operable to effect a comparison between the stored constant and accumulated value at that address. If the accumulated value is not equal to the constant, the accumulated value is incremented by one and both values are stored in their respective registers at their original address; if the two compared values are equal, a control signal is produced and the constant is stored but the corresponding accumulator register is reset to zero.
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