| 摘要 |
A circuit is disclosed for controlling and regulating the speed of a D.C. motor fed from a single-phase A.C. supply. A full-wave power bridge using two diodes and two silicon controlled rectifiers (SCR's) supplies unfiltered rectified A.C. to the motor. A first programmable unijunction transistor (PUT) is used to trigger the SCR's in response to a timing capacitor voltage applied to its anode. The timing capacitor is charged from a zener-regulated, full-wave bridge source through a speed-control resistor and thus provides triggering of the SCR's at a phase angle determined by said speed-control resistor. To obtain consistent triggering at the same phase angle, a second PUT is used to reset the voltage on the timing capacitor to zero at the end of each half cycle of the A.C. voltage to insure that the initial charge condition of said capacitor is always the same. A third SCR is triggered into conduction at the same that each bridge SCR is triggered and is connected to clamp the zener-regulated voltage to a low value during the conduction period. This prevents the possibility of the timing capacitor recharging to the trigger voltage a second time in the same half cycle and thus causing false triggering. |
