发明名称 INTEGRATED CIRCUIT FOR ELECTRONIC CLOCK
摘要 PURPOSE:To execute exactly an ordinary operation, and also to decrease the number of terminals, by constituting so that a test signal from a test state setting circuit can be generated only at the time of reset. CONSTITUTION:At the ordinary time, an output of an oscillating circuit 1 is frequency-divided 2, and the time is displayed 4 through a driving circuit 3. In this case, a test state setting circuit 7 is in a reset state. In case of executing a test, a reset terminal RS is made H, a storing circuit 7a is released from a reset state, and a state of the storing circuit corresponding to a test item is set from an input termial CL, by which a test signal is generated from a test signal generating circuit 7b.
申请公布号 JPS58204386(A) 申请公布日期 1983.11.29
申请号 JP19820087802 申请日期 1982.05.24
申请人 DAINI SEIKOSHA KK 发明人 EJIRI AKIRA
分类号 G01R31/28;G01R31/3185;G04D7/00 主分类号 G01R31/28
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