| 摘要 |
<p>A receiver circuit ensures that pulse code modulated data is sampled at the correct rate. The synchronising signal is digitally added to the information signal to generate a DC signal that indicates any variation in transmission frequency. The receiver sends signals via a demodulator a synchronising circuit, and tuning circuit to a data output. The tuning circuit consists of a modulo 2 binary adder that sums the information signals with a synchronising signal, chosen to have a frequency twice that of the data transmission rate. Ideally the synchronising signals occur in the middle of the data and provide a null DC signal. If the frequency of data transmission changes, a positive or negative DC signal appears.</p> |
