Debug interface for multiple CPU cores

摘要

A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of several types of packets such as a Second Access Bus (SAB) packet and Debug Access Bus (DAB) packet. The cores include specified resources and non-specified resources. A core that executes a transaction in response to a SAB packet accesses a non-specified resource and a core that executes a transaction in response to a DAB packet accesses a specified resources. A debug specification identifies the specified resources as being accessible by a debug controller. The debug specification does not identify the non-specified resources as being accessible by the debug controller.

主权项

1. A system, comprising:
resources within processor cores that are each in communication with a debug bus such that the cores receive packets over the debug bus,
the cores executing transactions in response to the packets,the packets each being a type of packet selected from a group that includes Second Access Bus (SAB) packets and Debug Access Bus (DAB) packets,the resources including specified resources and non-specified resources, a core that executes a transaction in response to a DAB packet accesses a specified resource and a core that executes a transaction in response to a SAB packet accesses a non-specified resource,
a debug specification identifies the specified resources as being accessible by a debug controller but does not identify the non-specified resources as being accessible by the debug controller.