| 摘要 |
PURPOSE: A memory device is provided to reduce unwanted power consumption while rapidly performing a write operation which inverts a stored content. CONSTITUTION: A memory cell(MC) includes a storage cell(SC), a reproduction circuit(RK) and a plurality of pass transistors(MN9,MN10,MN11 and MN12) in the form of an NMOS transistor. The memory cell(MC) further includes a write data bit line(41), a write complement bit line(42), a write word line(31), a write complement word line(32) and a read word line(33). The transistors(MN9,MN10) are connected in series between a node(N1) and the write data bit line(41), and have gates connected to a write control line(44) and the write word line(31), respectively. A potential corresponding to the exclusive OR of the write data bit line(41) and the write data complement bit line(42) is applied to the write control line(44). The write data bit line(41) and the write data complement bit line(42) which are not used for a write operation are precharged to the same potential to turn off the transistor(MN9).
|
