| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an overlay vernier of a semiconductor element that not only prevents pattern defects due to a level difference thereof caused when carrying out the exposure for forming a sub vernier but also accurately measures the alignment degree thereof. <P>SOLUTION: The overlay vernier of the semiconductor element includes an inner space in a scribe region of a semiconductor substrate 100, and a square frame like main vernier 101 whose frame portion is protruded. Further, the overlay vernier includes a sub vernier pad 103 whose height is the same as that of an upper end portion of the main vernier formed in the inner space of the main vernier 101, and the sub vernier 104 formed on the sub vernier pad 103. More specifically, the sub vernier 104 is formed on the sub vernier pad 103 formed in the inside region of the main vernier 101 so that the level difference of the main vernier pattern formed on the scribe region of the semiconductor substrate 100 is eliminated. This not only prevents the pattern defects due to the level difference caused when carrying out the exposure thereof for forming the sub vernier 104 but also accurately measures the alignment degree thereof. <P>COPYRIGHT: (C)2008,JPO&INPIT |
