| 摘要 |
<p>PURPOSE:To eliminate a delay time during the selection of word lines and to achieve a high speed memory access by dividing a memory cell into two parts and by making the word lines a H level through the use of individual decoders. CONSTITUTION:Word lines WR0 to WR511 and WL0 to WL511 are made to an H level in sequence and the contents of plural memory cells 10a and 10b, which are connected to the word lines, are outputted to bit lines B0 to B511. Then, the memory cell is devided into two blocks 10a and 10b and at the same time the decoder, which makes word lines to an H condition, is divided into two groups 20a and 20b. Then, the word lines are divided into two groups R and L and the H conditions are changed in the two blocks. When an access takes place against the memory cell 10b while one word line WRi is in an H condition, the word line WLj against the memory cell 10a, which is located in the other block L and doing the next read out, is kept in an H condition. Therefore, the data rising time in the bit line during a word line change is eliminated.</p> |
