发明名称 LANNOJIKOKUDOKISOCHI
摘要 PURPOSE:To perform time synchronization with high accuracy by measuring transmission delay time, and correcting a time synchronizing frame by a time correction frame using a measured value. CONSTITUTION:An SD detection circuit 3 detects an SD(start delimiter) representing the leading position of the time synchronizing frame inputted from a LAN controller 1 as a transmission data signal S1. A counter control circuit 4 measures a time until the SD is detected after the transmission request of the time synchronizing frame is issued from a count number, and measures the transmission delay time. A CPU supplies transmission delay time information to the controller 1, and the controller 1 sets the delay time information on the time correction frame, and transmits it to a reception side. The reception side, when receiving the time correction frame, corrects a time based on the content of the frame, and completes a synchronizing operation after transmitting a reception response signal.
申请公布号 JPH04273737(A) 申请公布日期 1992.09.29
申请号 JP19910055640 申请日期 1991.02.28
申请人 TOSHIBA CORP 发明人 KANO TATSUYA
分类号 H04L7/00;H04L12/40 主分类号 H04L7/00
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