Virtualization across physical partitions of a multi-core processor (MCP)

摘要

A generic microprocessor architecture is provided with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

主权项

1. A multi-core processor, comprising:
a set of main processing elements, each configured to request a set of sub-processing elements from a logical group of sub-processing elements, the set of main processing elements comprising:
a first main processing element located in a first physical partition,a second main processing element located in a second physical partition, anda third main processing element located in a third physical partition, wherein the logical group of sub-processing elements comprises: a first sub-processing element located in the first physical partition, a second sub-processing element located in the second physical partition, and a third sub-processing element located in the third physical partition; and a first virtualized control thread generated by the first main processing element, the first virtualized control thread associating the second main processing element of the second physical partition with the logical group of sub-processing elements; wherein each of the first main processing element, the second main processing element, and the third main processing element, is configured to log events taking place at each of the first sub-processing element, the second sub-processing element, and the third sub-processing element.