发明名称 Treatment method of electrodeposited copper for wafer-level-packaging process flow
摘要 A method of treating a copper containing structure on a substrate is disclosed. The method includes electrodepositing the copper containing structure on a substrate, annealing the copper containing structure, and forming an interface between a pad of the copper containing structure and a solder structure after anneal. The interface can have improved resistance to interfacial voiding. The copper containing structure is configured to deliver current between one or more ports and one or more solder structures in the integrated circuit package. Annealing the copper containing structure can move impurities and vacancies to the surface of the copper containing structure for subsequent removal.
申请公布号 US9412713(B2) 申请公布日期 2016.08.09
申请号 US201313744335 申请日期 2013.01.17
申请人 Novellus Systems, Inc. 发明人 Buckalew Bryan L.;Mayer Steven T;Ponnuswamy Thomas;Porter David
分类号 H05H3/00;H01L23/00;H01L21/67;C25D3/38;C25D5/10;C25D5/50;H01L21/288;C25D3/60;C25D17/00 主分类号 H05H3/00
代理机构 Weaver Austin Villeneuve & Sampson, LLP 代理人 Weaver Austin Villeneuve & Sampson, LLP
主权项 1. A method of treating a copper containing structure in an integrated circuit package, comprising: electrodepositing copper on a substrate to form a copper containing structure, wherein the copper containing structure includes at least 90 weight percent of copper, wherein the copper containing structure is configured to deliver current between one or more ports and one or more solder structures in the integrated circuit package; annealing the copper containing structure prior to forming an interface with the copper containing structure and one of the solder structures; and after annealing the copper containing structure, forming the interface between the copper containing structure and one of the solder structures, wherein the interface between the copper containing structure and the solder structure has improved resistance to interfacial voiding at the interface.
地址 Fremont CA US