发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To reduce any soft errors being made on alpha line by a method wherein, in a DRAM, a metallic interconnection (data line) to be a source of alpha line is provided on a position not overlapped with a depletion region formed on a semiconductor substrate on the sidewall of fine pore of a data storing capacitor element. CONSTITUTION:A data storing capacitor element C of memory cell is composed of a semiconductor substrate 1, fine pore (or fine groove) 2, a dielectric film 3 and a MIS type capacitor element comprising a plate electrode 4 while a switching MISFT is composed of the semiconductor substrate 1, a gate insulating film 6, a gate electrode 7 and an N<+> type semiconductor region 8. A data line 11 electrically connected to a semiconductor region 8 through a contact hole 10 is provided on a position not overlapped with a depletion region (d) formed on the semiconductor substrate 1 on the sidewall of fine pore 2. Through these procedures, the flying stroke of peak alpha rays passing through the depletion region (d) can be shortened while reducing the minor carriers happen to be arrested by the capactior element C to prevent any soft errors from being made.
申请公布号 JPS62169473(A) 申请公布日期 1987.07.25
申请号 JP19860010079 申请日期 1986.01.22
申请人 HITACHI LTD 发明人 OOSHIMA KAZUYOSHI
分类号 H01L21/768;G11C11/34;H01L21/8242;H01L23/522;H01L27/10;H01L27/108 主分类号 H01L21/768
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