发明名称 Method of manufacturing semiconductor device having impurity region under isolation region
摘要 In formation of a source/drain region of an NMOS transistor, a gate-directional extension region < 41a> of an N<SUP>+</SUP> block region < 41 > in an N<SUP>+</SUP> block resist film < 51 > prevents a well region < 11 > located under the gate-directional extension region < 41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region < 11 > having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode < 9 >, can be formed as a high resistance forming region <A 2 > narrower than a conventional high resistance forming region <A 1 >. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
申请公布号 US2008050864(A1) 申请公布日期 2008.02.28
申请号 US20070907857 申请日期 2007.10.18
申请人 发明人 MAEDA SHIGENOBU;IWAMATSU TOSHIAKI;IPPOSHI TAKASHI
分类号 H01L21/02 主分类号 H01L21/02
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