| 摘要 |
<p>The invention discloses a cross connect architecture for SDH signals, in which the input stage is composed of parallel TS switch blocks (TSW-SSW), the centre stage (MSW) is composed of parallel time and space switch blocks (STS; TxT-S) and the output stage is a symmetrical mirror image of the input stage. It is advantageous that the centre stage have a large number of blocks (MSW) relative to the minimum need, even double as many, whereby in practice a non-blocking switching network is obtained. All the switch blocks have doubled control memories, which ensure interference-free reconnections.</p> |
