| 摘要 |
<p>PURPOSE:To realize an automatic correction for the speed of synchronization at the receiver side, by sending a synchronous character from the transmitter side and prior to the transmission of data. CONSTITUTION:A start bit detecting circuit 1 detects the fall of a start bit ST in a transmited signal (a) and then starts counters 3 and 4. The value of the counter 3 shows the time width of the bit ST; and the value of an integrating circuit 5 that adds the count value of the counter 4 shows the time width of the number of bits of a synchronous character plus one. When a synchronous character detecting circuit 7 identifies that the input signal (a) is equal to a synchronous character, the circuit 5 obtains a sampling period (d) of the input data from the integral value and gives it to a sampling circuit 6. At the same time, the circuit 6 receives a synchronous character detection signal (e) from the circuit 7 and carries out a sampling of the input data based on the synchronization of sampling until the next synchronous character is received.</p> |
