发明名称 MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To simplify characteristic check, by providing an N-type transistor and a P-type transistor on the same semiconductor substrate when an IC in a C-MOS master slice method is formed, and providing not only the gate electrodes but also source and drain electrodes for test on the transistors. CONSTITUTION:An N-type Si substrate 31 is divided into N-type and P-type transistor forming regions 34 and 35 by a field oxide film 33. A P-type well region 32 is diffused and formed in the region 34. Resist masks having openings are mounted on gate oxide films 36, which are deposited on the regions 34 and 35. N-type impurity ions are implanted in the region 32 in the region 34, and an implanted layer 39 is provided. In the region 35 of the substrate 31, P-type impurity ions are implanted, and an implanted layer 42 is formed. Thereafter, the masks are removed. Gate electrodes 44 and 44' are provided on the regions 34 and 35 through the films 36. Under this state, orders are waited. Electrodes 45 and 45', which are also used for test, are formed in a region 46 comprising the region 39 and a region 47 comprising the region 42 beforehand.
申请公布号 JPS61220454(A) 申请公布日期 1986.09.30
申请号 JP19850062313 申请日期 1985.03.27
申请人 TOSHIBA CORP 发明人 ONO JUNICHI
分类号 H01L27/092;H01L21/265;H01L21/8238;H01L27/118;H01L29/78 主分类号 H01L27/092
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