DIGITAL SIGNAL PROCESSING CIRCUIT

摘要

PURPOSE:To perform the signal processings corresponding to various sampling frequencies without damaging the normal operation of a circuit operated at a prescribed operating frequency by controlling the processing data taking-in operation at the timing synchronized with a specific timing signal. CONSTITUTION:A master clock MCLK is always supplied to a dynamic type flip flop for data storage. Switching of the sampling period of the digital signal coming to an input terminal D is detected based on a first timing signal TM1, and the new data take-in operation or the like in an input interface circuit is activated when the first timing signal TM1 and a second timing signal TM2 are made effective together. The second timing signal TM2 has the period which is an integer-number of times as long as the period of the first timing signal TM1. Thus, the signal processing corresponding to a desired sampling frequency is performed without changing the fundamental operating frequency of each part in the circuit.