| 摘要 |
PURPOSE: A clock buffer and a merged memory logic(MML) semiconductor device including thereof are provided to reduce the time spent in solving a fail of a delayer comprised in the clock buffer. CONSTITUTION: The clock buffer includes: a clock generator(233) generating a clock signal of different voltage level, when it is activated, from that of a clock signal from the external in response to the external clock signal; at least two delayers(271,272,273) which are connected electrically to the clock generator and delay the different clock signal with different delay time respectively; and switches(281,282,283) which are connected to output terminals of the delayers electrically, and control an output of the delayers in response to a control signal from the external. Each switch includes: a multiplexer having two input ports and one output port; and a control part controlling the multiplexer in response to the control signal.
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