| 摘要 |
PURPOSE:To attain high speed locking at training and to improve the stability of the system by providing an overflow control circuit and controlling a voltage controlled oscillator and a programmable counter so as to generate a received sampling clock. CONSTITUTION:An output of an overflow control circuit 103 is converted into an analog signal by a D/A converter 104, an analog low pass filter 105 limits the band of the analog signal and the input subjected to band limit is a control voltage of a voltage controlled oscillator 106. A programmable counter 107 frequency-divides an oscillating frequency of the oscillator 106 by 1/N (natural number) to generate a sampling clock 2. Furthermore, the counter 107 references a counter control signal 108 for each M[T] (M is a natural number and T is a predetermined period), and when the count is positive, the initial value of the counter is set to N-1 and when the value is negative, the initial value of the counter is set to N+1 to adjust the sampling phase. However, the counter 107 does not refer to the signal 108 after phase locking. |
