Shadow DRAM for programmable logic devices

摘要

A plurality of DRAM cells are used to store the state of the programmable points in the FPGA ("FPGA DRAM cells"). A shadow DRAM array holds duplicate data of the plurality of DRAM cells. A DRAM cell of the shadow DRAM array is sensed during a refresh cycle. In this manner the refresh cycle does not alter the logic configuration of its associated FPGA DRAM cell.