| 主权项 |
1. A programmable frequency divider to receive an input signal (Fvco) having a first frequency, and to generate an output signal (Ffb) having a second frequency, said programmable frequency divider comprising:
a divide input for receiving a divide ratio, wherein said divide ratio is representative of a number by which the frequency of said input signal (Fvco) is to be divided to generate said output signal (Ffb), wherein said divide ratio is between a lowest limit and a highest limit, said divide ratio being represented by a set of bits; a cascade of M frequency-dividing units coupled in series, said cascade comprising a lowest unit and a highest unit, with the remaining of the M units being disposed in series between said lowest unit and said highest unit, wherein the highest unit is the Mth unit, and the lowest unit is the first unit in said cascade, said lowest unit being coupled to receive said input signal (Fvco), wherein the range of values by which the frequency of said input signal can be divided by said cascade depends on the number of frequency-dividing units of said cascade that are operative, whereby said range of values is a first range if N successive frequency-dividing units of said M units are operative, but a second range, not equal to said first range, if (N−1) frequency-dividing units are operative, wherein each frequency-dividing unit in said cascade comprises:
a first input for receiving an input clock;a first output for providing an output clock to the next frequency-dividing unit in said cascade;a second output for providing a mode control signal to a previous frequency-dividing unit of said cascade; anda second input for receiving a corresponding bit in said set of bits, said corresponding bit having a logic level depending on said divide ratio, wherein the logic value received at said second input determines whether the frequency-dividing unit divides by a first factor or a second factor;a third input for receiving a mode control signal from said next frequency-dividing unit, wherein said mode control signal indicates when to use said second factor, instead of said first factor in dividing said input clock,wherein the mode control signal received by the highest operative unit is fixed at a pre-defined logic level; and a logic unit coupled to receive said input signal, the mode control signal from said lowest unit and a resetting mode control signal, said logic unit designed to generate said output signal, wherein said logic unit generates transitions of said output signal from a first level to a second level coinciding with period-defining edges of said mode control signal from said lowest unit, wherein said logic unit generates transitions of said output signal from said second level to said first level coinciding with rising edges of said resetting mode control signal, wherein said divide ratio is at a first value in a first duration and a second value in a second duration, wherein said first value causes all of said frequency-dividing units to be operative for corresponding division operation, and wherein said second value causes one or more of said frequency-dividing units including said highest unit be non-operative for a corresponding division operation, wherein a mode control signal generated by only a same unit of said frequency dividing units is used as said resetting mode control signal in both of said first duration and said second duration. |
