发明名称 DELAY TIME CALCULATING METHOD AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT BY USING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a delay time calculating method considering a shield effect, which can be applied to the delay time calculation of a semiconductor integrated circuit composed of plural electronic circuit cells and a plurality of wiring. SOLUTION: In the method for calculating the delay time of each of electronic circuit cell by replacing a circuit connected to the output terminal of an electronic circuit cell with one effective load capacity, in processing 111, a load parameter, with which the circuit connected to the output terminal is expressed by an equivalent circuit including a resistance element, capacitance element or inductance element, is inputted and in processing 101, each of capacitance element connecting node voltages of the equivalent circuit during transition time until the voltage of the output terminal reaches a delay time definition voltage is calculated. In processing 103, the effective load capacity is calculated from each of capacitance element connecting node voltages and in processing 104, delay time 112 of the electronic circuit cell is calculated from the effective load capacity. Therefore, the delay time of the semiconductor integrated circuit can be highly accurately calculated at high speed.
申请公布号 JP2002163324(A) 申请公布日期 2002.06.07
申请号 JP20000360657 申请日期 2000.11.28
申请人 HITACHI LTD 发明人 OKUBO MICHIO
分类号 G01R31/28;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/28
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