| 发明名称 |
Eeprom having erasing gate electrode patterns formed to intersect source region patterns and method for manufacturing the same. |
| 摘要 |
<p>A memory cell array is formed of a plurality of nonvolatile memory cell transistors arranged in a matrix form. The patterns of the control gate electrode (106) and the source region (102, 102 min ) of each memory cell transistor are formed in parallel and the pattern of the erasing gate electrode (105) is formed to intersect the source region and control gate electrode patterns. A field oxide film is formed in an intersecting portion between the source region (102, 102 min ) and the erasing gate electrode (105).</p> |
| 申请公布号 |
EP0378227(A1) |
申请公布日期 |
1990.07.18 |
| 申请号 |
EP19900100595 |
申请日期 |
1990.01.12 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA;TOSHIBA MICRO-ELECTRONICS CORPORATION |
发明人 |
TAURA, TADAYUKI C/O INTELLECTUAL PROPERTY DIVISION;ASANO, MASMICHI C/O INTELLECTUAL PROPERTY DIVISION;KANEBAKO, KAZONORI C/O INTELLECTUAL PROP. DIVISION;IWAHASHI, HIROSHI C/O INTELLECTUAL PROP. DIVISION |
| 分类号 |
H01L21/8247;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
H01L21/8247 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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