Monitoring arrangement for data transmission in bus communication operations - has access to bus controlled such that errors in data or addresses are identified

摘要

A data processor unit (VE) with a CPU and memory is connected via a bus drive stage (BE) to a system bus (SYB) that supports a number of modules (E1-E3), each with drive stages (B1-B3). Control of the modules is such that only one may access the system bus at a specific time. The modules are identified by addresses and are defined as input and output units. The central processing unit (VE) communicates with the modules that are programmed for a two stage access cycle. Each stage of the access cycle requires the generation of an acknowledgement signal before proceeding. ADVANTAGE - Identifies data and address errors in access process.