| 摘要 |
A process of fabricating an array of floating gate memory devices on a substrate comprises forming elongated spaced apart parallel ion implanted field implant regions in the substrate, forming elongated spaced apart parallel buried bit lines in the substrate orthogonally directed relative to the field implant regions, forming field oxide regions over the buried bit lines and field implant regions, and growing a silicon dioxide gate oxide layer having a thickness of from approximately 80 ANGSTROM to approximately 300 ANGSTROM between the field oxide regions, forming a plurality of first gate members from a first layer of polysilicon, the first gate members being disposed over the gate oxide layer, forming a layer of interpolysilicon dielectric over the first gate members having a thickness of approximately 150 ANGSTROM , forming elongated second gate members from a second layer of polysilicon over the layer of interpolysilicon dielectric and over the first gate members, the second gate members extending generally perpendicular to buried bit lines.
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