| 摘要 |
PROBLEM TO BE SOLVED: To reduce a time penalty with sign extension as to partial product addition by parallel multipliers. SOLUTION: A partial product adder 15 which adds four partial products P0, P1, P2, and P3 that are binary numbers represented as complement of '2' and differ in weight from one another comprises a carry storage adder 20 constituted by arraying 4:2 compressors. In each 4:2 compressor, a W input among the four inputs shows the shortest propagation delay and Y and Z inputs constitute a critical path. So that the 1st partial product P0 having the least weight is sign-extended, a logic circuit 30 sets the logical operation value between the value of the sign digit P0s of the 1st partial product and the value of the sign digit P1s of the 2nd partial product having the 2nd small weight to digits higher in order than the sign digit P0s of the 1st partial product, and while the sign-extended 1st partial product P0 is allocated to the W input of the carry storage adder 20, the values of the high-order digits of the Z input regarding the 2nd partial product P1 are fixed at 0. |
