TRIPLE WELL FLOATING GATE MEMORY AND OPERATING METHOD WITH ISOLATED CHANNEL PROGRAM, PREPROGRAM AND ERASE PROCESSES
摘要
<p>A floating gate memory cell having a first well (31), second well (30) source/drain regions (13/14), a floating gate (15), a control gate (17) and circuits to induce tunneling of electrons from the floating gate into the channel area.</p>
