Dynamically programmable bus arbiter with provisions for historical feedback and error detection and correction

摘要

An arbitration circuit that uses a unique history register that is combined with a value representing bus requests to index into a table. All possible combinations of history register requests are stored in the table along with a corresponding grant. A block of the table is selected by the history register, and then the request is used to index into the block to determine which request receives a grant. The grant is then shifted into the history register. Advantageously, more than one table may be stored in memory which can be selected by an arbiter controller.