发明名称 |
RECEIVER OF STILL PICTURE SIGNAL |
摘要 |
PURPOSE:To fetch and read the still picture signal to and out of a memory in synchronizing accurately with said signal by detecting the coincidence between an address allocated previously and an address sent from a CPU via a bus. CONSTITUTION:A CPU18 delivers a certain address where an address coder 35 is fixed to an address line 26. A circuit 15 decodes said address and outputs a decoding pulse to an AND circuit 31 and an OR circuit 33 respectively. The pulse supplied to the circuit 33 is supplied as it is as a clock pulse of a 254-bit shift register 34 of a buffer memory 21 to read out a bit of the memory contents. the read-out memory contents are outputted to the circuit 31. In this case, the above-mentioned decoding pulse is applied to the other input of the circuit 31. Therefore the memory contents are outputted as they are to a data line 25 of the CPU18. The above-mentioned actions are repeated and the CPU18 can read successively the bits of the identification signal contained in a still picture signal. |
申请公布号 |
JPS60132480(A) |
申请公布日期 |
1985.07.15 |
申请号 |
JP19840153009 |
申请日期 |
1984.07.25 |
申请人 |
HITACHI SEISAKUSHO KK |
发明人 |
HIRAHATA SHIGERU;TAKEZAWA TERUHIRO;HIRAMATSU KIYOSHI |
分类号 |
H04N7/025;G09G5/00;H04N7/03;H04N7/035;H04N7/083;H04N7/087;H04N7/088 |
主分类号 |
H04N7/025 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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