FREQUENCY DIVIDING CIRCUIT, SERIES-PARALLEL CONVERSION CIRCUIT USING THE CIRCUIT AND SERIAL DATA TRANSMISSION AND RECEPTION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To frequency-divide the frequency of a reference clock to one in an integer except for n-th power of '2' by outputting one of output signals of a logic gate circuit as a signal obtained by frequency-dividing the reference clock signal into 1/n. SOLUTION: D-type flip flops F/F1-F/F4 and F/FF0 where respective reference clocks CK are inputted to a clock terminal and the latch operations of data signals inputted to a data terminal in synchronizing with the rise of the reference clocks CK are executed are installed in a ring form. A NAND gate Gi setting the output signals of the front stage flip flop F/Fi and a reset signal RESET to be input signals and an inverter INVi setting the output signal of the NAND gate Gi to be the input signal are installed. An inverter INVO is connected to the output terminal of the flip flop F/F0. A signal obtained by inverting the output of the NAND gate G1 connected to the output terminal of the flip fop F/F1 by an inverter INV1 is outputted as a frequency clock BCK.