| 摘要 |
A matrix display has pixels 2 each including a programmable memory element 30 arranged in parallel across capacitance 28. The voltage on the capacitance controls a display element 25. The arrangement can be run in a normal mode, with all of the memory elements 30 in a high resistance state so that the matrix display can be driven dynamically. Alternatively, in a static (low power) mode of operation, the memory elements 30 are programmed with a static image which may be displayed without driving the data lines 6.
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